A 10GHz With Low Power And Low Noise Figure Amplifier Using 0.18/spl mu/m CMOS Technology

The purpose of this work is to explore the optimum LNA design that input impedance match, gain, noise figure, linearity, and power consumption, in this LNA design operating at the 10GHz has been simulated based on a TSMC 0.18-mum RF CMOS process. This paper presents a 10 GHz operation is designed and implemented in a standard cascode LNA technology for an 802.16a application. The LNA exhibits a noise figure of 2.4dB, power gain of 15.8-dB, input return loss of 15.7dB, 1dB compression point of -20.3dBm The power consumption is 18.9mW at Vcc = 1.8 V