Strained-si and advanced channel materials on insulator: challenges and opportunities

Integration of advanced high transport channel materials into Si-based CMOS devices holds great promises for CMOS scaling beyond Moore's Law. In this article, various heteroepitaxy approaches and structures for advanced channel material fabrication in "on-insulator" structures was discuss, including both global and localized epitaxy techniques with strained-Si, Ge, III-V etc. The limits, challenges and potential opportunities are addressed