High-speed and large noise margin tolerance E/D logic gates with LDD structure DMTs fabricated using selective RIE technology

The authors describe a novel design concept for enhancement (E) and depletion (D) mode FET formation using i-AlGaAs/n-GaAs doped-channel hetero-MISFET (DMT) and a novel self-aligned gate process technology for submicrometer-gate DMT-LSIs based on E/D logic gates. 0.5- mu m gate E-DMTs (D-DMTs) with a lightly doped drain (LDD) structure show an average V/sub t/ of 0.18 (-0.46) V, a V/sub t/ standard deviation of 22.6 (24.9) mV, and a maximum transconductance of 450