A 0.5- mu m-gate GaAs/AlGaAs inverted HEMT IC-multiplier and D/A converter

A gate recess process for a 0.5- mu m I-HEMT (inverted high electron mobility transistor) has been developed. A drain conductance for the 0.5- mu m I-HEMT as small as 2 mS/mm was achieved, indicating a small short-channel effect. The threshold voltage uniformities were studied in microscopic and macroscopic areas in a 2-in wafer. The uniformities are very high, i.e. the standard deviations of microscopic and macroscopic areas are 10 and 30 mV, respectively, at a threshold voltage of 0.1 V. An 8*4 parallel multiplier was fabricated, and a multiplication time of 1.67 ns was obtained at room temperature. An 8-b digital/analog converter (DAC) was fabricated and operated at a clock rate of 1.2 GHz. The DC linearity of the DAC is better than 0.18 LSB. These results confirm that an I-HEMT is very well suited for high-speed integrated circuits.<
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