High Throughput, low cost, Fully Pipelined Architecture for AES Crypto Chip

Reprogrammable devices such as Field Programmable Gate Arrays (FPGA's) are highly attractive options for hardware implementations of encryption algorithms. Several papers described efficient architectures for ASICs and FPGAs. Various approaches for efficient hardware implementation of the Advanced Encryption Standard algorithm based on architectural optimization and algorithmic optimizationfor different modes are discussed and implemented. This paper proposes Compact,Memory less, high-speed hardware architectures for the Rijndael AES Encryptor/Decryptor, with combined data path, resource sharing and logic optimization for novel networking applications. Architectural optimization exploits the strength of pipelining, loop unrolling and sub-pipelining. Speed is Increased by processing multiple rounds simultaneously at the cost of increased area. Algorithmic optimization exploits algorithmic strength inside each round unit. Various methods such as Resource sharing and Common sub expression elimination method for realizing various transformations in each round unit are presented to reduce the critical path and area issues between encryptor and decryptor. advantage of sub-pipelining can be further explored by eliminating the unbreakable delay incurred by look-up tables in the conventional approaches, the widely used implementation of S-box, which uses combinational logic only. We explore the use of subfield arithmetic for efficient implementations of Galois Field arithmetic such as multiplication and inversion.. Our technique involves mapping field elements to a composite field representation and a representation technique which minimizes the computation cost of the relevant arithmetic.