Design Methodology for CMOS Low-Noise Amplifiers Using Power Matching Techniques

In this paper, a methodology in designing CMOS Low-Noise Amplifiers (LNAs) is proposed. Three power-matching techniques are considered in the design of the LNA. These are: (1) matching for maximum available gain, (2) matching for a constant gain, and (3) matching for stability. Using a 0.25 μm CMOS process, several LNA circuits employing the common-source topology with cascode configuration are designed, implemented, fabricated, and tested. The performance of LNA circuits designed using the three different techniques are characterized. Simulation and actual measurement results are also compared and analyzed to determine the capability of the simulator to predict the LNA's overall performance at radio frequencies.