Charge Build up and Breakdown in Thin Sio2 Gate Dielectrics

SiO2 layers with low defect densities have been grown in a double-walled oxidation tube, for use as thin gate dielectrics in MOS IC's. Under all high-field stress conditions positively charged slow states are created at the Si-SiO2 interface. These can be neutralized by applying positive fields at the gate of an MOS device. Negative charge can also be generated, especially during a positive field stress. The total amount of generated charge is much less for polysilicon gate capacitors than for Al-gate capacitors. The time-to-breakdown in a wearout experiment could be extended by periodic application of a positive gate voltage. This also caused neutralization of the slow states. However, it had no influence on the high-field breakdown distribution in a fast voltage ramp experiment. It is suggested that interface rather than bulk phenomena dominate trap generation and charge build-up during the high-field stresses which induce oxide breakdown.