A Custom-made Algorithm-Specific Processor for Model Predictive Control

This paper presents an algorithm-specific processor for embedded model predictive control (MPC). After analyzing the computational cost of MPC, via profiling, we observe that the optimizations associated with MPC are dominated by operations on real matrices. To overcome this bottleneck we propose connecting a limited resource host processor with an algorithm-specific matrix processor, whose architecture is described. The matrix processor uses a 16-bit logarithmic number system (LNS) arithmetic unit to carry out the required arithmetic operations. The proposed architecture is implemented using a hardware description language (HDL) and subsequently it is synthesized and emulated on a field programmable gate array (FPGA). The timing and area cost results are presented and analyzed