VHDL - The Language

The VHSIC hardware description language (or VHDL) provides a standard textual means of description for hardware components at abstraction levels ranging from the logic gate level to the digital system level. It provides precise syntax and semantics for these hardware components, enabling design transfer both within and among organizations. The language is designed to be efficiently simulated and natural for hardware designers. In addition, it allows designers to represent information outside the primary range of language coverage, although the initial toolset does not support simulation at those levels (switch level, for example). Finally, by not restricting designers to a particular hardware technology or design style, the language permits wide industrial usage.