DRAM macros for ASIC chips

DRAM macros in 4-Mb (0.8-/spl mu/m) and 16-Mb (0.5-/spl mu/m) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products. It is shown that the trench cells with capacitor plates by the grounded substrate are ideal structures as embedded DRAM's. The trench cells built entirely under the silicon surface allow cost effective DRAM and CMOS logic merged process technologies. In the 0.8-/spl mu/m rule, the DRAM macro has a 32-K/spl times/9-b configuration in a silicon area of 1.7/spl times/5.0 mm/sup 2/. It achieves a 27-ns access and a 50-ns cycle times. The other DRAM macro in the 0.5-/spl mu/m technology is organized in 64 K/spl times/18 b. It has a macro area of 2.1/spl times/4.9 mm and demonstrated a 23-ns access and a 40-ns cycle times. Small densities and multiple bit data configurations provide a flexibility to ASIC designs and a wide variety of application capabilities. Multiple uses of the DRAM macros bring significant performance leverages to ASIC chips because of the wide data bus and the fast access and cycle times. A data rate more than 1.3 Gb/s is possible by a single chip. Some examples of actual DRAM macro embedded ASIC chips are shown.<
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