A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects

This paper describes a low-swing on-chip interconnect signaling technique. A simple receiver circuit enables significant total energy and delay reduction compared to conventional repeaters over intermediate and global interconnects. A 5 mm minimum pitch global interconnect in 65nm CMOS technology using 1.1V supply exhibits a reduction of 56% in total energy, 21% in delay, and 86% in area.