Performance Enhancement via Laser Anneal-Based RS/D Reduction in PD/SOICMOS

Extrinsic source/drain series resistance (R
_S
D/) becomes a limiting factor as performance boosters, such as strain-Si and metal-gate/high-k gate stack that enhance the intrinsic MOSFET, are vigorously pursued and implemented in nanoscale CMOS (Ghani, et al., 2003). Non-melt laser spike anneal (LSA) (Feng et al., 2004) has been suggested (Shima, et al., 2004), (Fung et al., 2004) as a means to reduce R
_S
D/. In this paper, we present, for the first time, application of LSA to 35nm gate length, high-performance PD/SOI CMOS with dual etch stop layer (dESL) stressors and NiSi (Grudowski et al., 2006), showing 10% (4%) nFET (pFET) on-state current (I
_on
) enhancement and non-self-heated I
_on
=1520/1160muA/mum (880/630muA/mum) at V
_DD
=1.2V/1.0V