Performance of an Integrated 2.1 GHz Analog Predistorter

This paper presents the structure and measured results of a RF predistorter IC fabricated in a 0.35mum SiGe BiCMOS process. The IC implements a 5th-degree polynomial predistorter which has been used to linearize a 2.1 GHz LDMOS power amplifier. The measurement setup and results are described. Up to 20 dB cancellation is achieved in 2-tone measurements and up to 8 dB with WCDMA data. The circuit includes also output for the squared envelope signal that can be used as a baseband injection signal to cancel 2nd order distortion components that typically cause memory effects