Simplified performance modelling of hierarchical memory systems

We develop a simple analytical model for a memory hierarchy. This model allows us to accurately estimate the performance of a multi-level hierarchy using only the execution statistics of a single level cache. The benefit of this approach is that alternative designs can be rapidly evaluated to narrow the design space before undertaking detailed simulation. This modelling technique is validated by applying it to a two level cache system and comparing its predictions with the output of a two-level trace driven simulator. Three different cache designs are tested-write through/write through (WTWT), write back/write through (WBWT), and write through/write back (WTWB)-which test different write handling strategies for the first and second level caches. The model's results are accurate; predicted performance differs by typically less than 3% from that given by trace-driven simulation. Specifically, the model predicts that the write back/write through design gives the best performance, that increasing the block size for the first level cache can decrease system performance, and that the effect of increasing the second level cache size is more pronounced when the first level cache is larger.<
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