Triple-DES ASIC Module for a Power-Smart System-on-Chip Architecture

This paper presents new 3-DES architecture with current flattening support for increased resistance against power analysis attacks. Also, new pipelined architecture of the 3-DES algorithm is proposed and implemented using 0.18 mum CMOS technology. The paper presents synthesis and simulation results for the 3-DES ASIC implementation. The synthesis results have shown that 3-DES module occupies an area of 326K mum
²
and the average power consumption is 18.35 mW. In comparison with previous research, the proposed implementation occupies less area and consumes less power. Other results presented include average current and power simulations results using Synopsys Nanosim tool