The CHIP - A Design Guide for Reducing Substrate Noise Coupling in RF Applications

This article discusses a set of design guidelines to reduce the on-chip substrate noise coupling in RF and mixed signal applications. Measurement data is presented to compare the various signal isolation techniques. A design flow is calibrated to the measured data and is used to expand the design guide to include the effects of the geometrical and electrical parameters of the isolation structures as well as the frequency of operation on the isolation level. A set of guidelines is presented to the reader as a summary of the studied experiments