Combining the top-down approach with bottom-up advantages in logic synthesis

The current trend in logic synthesis of top-down ASIC designs has been towards offering the same advantages associated with bottom-up designs such as transistor level optimization with advanced algorithms. This paper proposes a method to exploit these benefits during logic synthesis. Top-down and bottom-up strategies are discussed and a way is shown how to combine both advantages of both methodologies. Results achieved with and without this methodology are compared. The comparisons exhibit the value of the new approach.<
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