A flexible repetitive CSD code filter processor unit in CMOS

We introduce a filter processor unit that realizes digital nonrecursive (FIR) and recursive (IIR) filtering with optimal selectable coefficient, data wordlength and filter order. This flexibility is achieved by combination of four identical filter modules. The design is carried out in a 1.0 /spl mu/ CMOS process; additionally a multiplier-free second order /spl Sigma//spl Delta/-modulator is implemented. It occupies a chip area of 87 mm/sup 2/.<
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