Design of a processor bus interface ASIC for the stream memory controller

The Stream Memory Controller (SMC) is an experimental memory interface which allows hardware-assisted memory access reordering for vector computations in order to maximize the efficiency of the system memory bus. This paper describes the design and test strategies for the SMC Processor Bus Interface (PBI) and FIFO logic ASIC. This IC is designed as part of a daughter card attachment to a 40 MHz Intel i860 system. The entire integrated circuit design was completed in a top-down design environment using VHDL for synthesis and a target process of 0.75 /spl mu/m. The design includes SRAM elements, combinatorial logic, and state machine components. This ASIC is the first in a series of ICs intended as a proof-of-concept of the SMC based system.<
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