Compact Implementation of a Sum-of-Sinusoids Rayleigh Fading Channel Simulator

The demanding performance requirements of wireless applications along with the increasing computational complexity of baseband algorithms have greatly increased system simulation loads. A channel simulator is an essential component in the development and accurate performance evaluation of wireless systems. This paper presents an improved hardware implementation of a Rayleigh fading channel simulator. The simulator uses only 1% of the Xilinx Virtex2P XC2VP100-6 field-programmable gate array (FPGA) and operates at up to 211 MHz, generating 211 million accurately distributed complex fading coefficients per second. Our fading channel simulator is 506 times faster than a software-based simulator written in C language running on a 3.4-GHz Pentium 4 processor. The fading Q simulator layout in 90-nm CMOS technology occupies 356,409 mum
²
of silicon area when the operating rate target is 500 MHz