Optimizing Filter Order and Coefficient Length in the Design of High Performance Fir Filters for High Throughput FPGA Implementations

This paper discusses the tradeoff between filter order and coefficient length in the design and implementation of high-performance filters in field programmable gate arrays (FPGAs). Non-minimum order FIR filters are designed for implementation using canonical signed digit (CSD) multiplierless implementation techniques. By increasing the filter order, we are able to decrease the length of the coefficients without reducing the filter performance. Thus, an overall hardware savings can be achieved. In addition, we consider the use of overly-stringent specifications combined with quantization and increased order to improve the filter implementation