Plated Wire Content-Addressable Memories with Bit-Steering Technique

This report describes a new concept of content-addressable memory (CAM) implemented with plated wires and the bit-steering technique. The 5-mil plated wires are insulated with a thin (0.2 to 0.3 mil) coat of polyurethane, and imbedded in a copper plane. A memory array is formed by means of a simple orthogonal arrangement of plated wires and an overlay of copper straps. Because of the low loop impedance (2 to 5 ohms depending on the design but uniform to within ± 5 percent for a given design) formed between an insulated plated wire and the copper plane, a loop current of the order of 30 mA can be generated by pulsing a pair of straps. This current is used to transfer information from one bit position to another bit along the same plated wire. Consequently, logic manipulations can be performed within the memory array. The resolve operation is executed in the array where a binary address tree is stored. The addresses of matched words are obtained via the sieving action of the tree. With a complementary address tree added to this resolve area, the addressed READ/WRITE operations are executed by first searching for the given address and then READ/WRITE on the matched word. The search cycle time of a CAM of 4096 words, 40 bits per word, is estimated to be about 1 to 2 μs, based upon experimental results. The resolve time is about 1.5 μs for any one of the 4096 addresses.