A Low Power Mobile Camera Processor Design with SubLVDS Interface

A mega pixel image signal processor (ISP) with low voltage differential serial interface is presented. subLVDS interface has lower voltage swing and lower power consumption advantages over a normal LVDS interface. Both subLVDS driver and receiver are implemented in this ISP chip to reduce the I/O pin count. A synchronization layer is designed to cover both non-compressed and compressed image data transfer on the high-speed serial data link. This chip is designed with a pure logic process in 0.18 mum CMOS technology. The subLVDS driver can operate at a transfer rate up to 625Mbps