A 667MT/s 10.7GB/s Multiprocessor Bus Interface

A 130nm 1.2V GTL bus interface with compensated slew rate and termination achieves 667MT/S 10.7GB/S data rate in a 3-load MP environment. The design utilizes preboost and postboost methods, current steering circuit to minimize simultaneous switching noise and negative hysteresis to speed up the common-clock delay. The design also incorporates system-level I/O loopback for system timing marginality test