Fast $V_{\rm th}$ Instability in $\hbox{HfO}_{2}$ Gate Dielectric MOSFETs and Its Impact on Digital Circuits

Fast component of V
_th
instability in MOSFET with HfO
₂
gate dielectric is systematically measured and characterized. A charge-trapping/detrapping model is used to simulate the V
_th
instability with overall agreement with the experiments. Experimental and modeling data provide and predict the fast V
_th
shift under both static and dynamic stress conditions. These data are incorporated into HSpice circuit simulation to evaluate the impact of V
_th
shift on the performance of digital circuit in realistic situations. Considering the properties of the fast V
_th
instability, circuit performance can be optimized by circuit design in addition to process improvements. This should be included to the guideline of process development and circuit design for future CMOSFET digital systems