Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs

The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive different channels at different data rates. Examples of such ATEs include the Agilent 93000 series tester based on port scalability and the test processor-per-pin architecture and the Tiger system from Teradyne. The number of tester channels with high data rates may be constrained in practice, however, due to ATE resource limitations, the power rating of the SOC, and scan frequency limits for the embedded cores. Therefore, we formulate the following optimization problem: Given two available data rates for the tester channels, an SOC-level test access mechanism (TAM) width W, an upper limit V (V