CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:$\hbox{Ni}_{2}\hbox{Si}$, and $\hbox{Ni}_{31}\hbox{Si}_{12}$) on HfSiON

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni
₃₁
Si
₁₂
FUSI gates on p-channel MOS (PMOS) with good V
_t
control to short gate lengths (L
_G
=50 nm, linear V
_t
of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni
₂
Si or Ni
₃₁
Si
₁₂
on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni
₂
Si or Ni
₃₁
Si
₁₂
FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% I
_on
improvement at I
_off
=100 nA/mum) was obtained for Ni
₃₁
Si
₁₂
compared to Ni
₂
Si FUSI gates, as well as a V
_t
reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS