A current testing for CMOS static RAMs to reduce testing costs

This paper presents a methodology to reduce the testing costs of a CMOS static RAMs (SRAMs), based on a current testing. In this test method, the structure of SRAMs is modified so that all the cells can be driven simultaneously. A fault in the memory cell array can be detected by only observing the abnormal current. Since the whole cell array could be treated as if it were a single cell, the length of the test sequences is not dependent on the size of the memory cell array and must be very short.<
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