Performance analysis of channel sharing in multistage ATM switching networks

An efficient algorithm based on convolutions and Fourier transforms is proposed for generating the transition matrix for a general class of discrete time queuing systems. The algorithm is illustrated with the analyses of G/sup [x]//D/1-S and D/sup [x]//D/sup [y]//h-S queuing systems. Using these models, a performance analysis of channel sharing in asynchronous transfer mode (ATM) switches is presented. In addition to internally nonblocking switches, self-routing multistage networks with the Benes topology are considered. With an appropriate self-routing algorithm based on randomization, these multistage networks are provably immune to internal congestion problems, can have arbitrarily low blocking probabilities, and can be significantly less expensive than internally nonblocking networks. It is shown that for equivalent hardware (i.e., gate-array integrated circuits), channel sharing allows multistage networks to carry significantly more traffic than the Batcher-Banyan and other internally nonblocking switches.<>