A high speed embedded cache design with non-intrusive BIST

This paper describes a 155 MHz wide-word cache design and its test integration features. Design techniques for high speed CAM with single ended match line sensing and highly integrated RAM are described. A new cache BIST algorithm based on the SMARCH algorithm is presented. New techniques are described for the insertion of cache BIST access points into a high speed data path without compromising mission mode performance. Performance results of cache memory used for telecommunications microprocessor applications with 1 Kb of CAM referencing a 5 Kb RAM are presented.<
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