A practical constant time sorting network

The authors propose a novel VLSI sorting network implementing Leighton's column sort. The network is mech-based and modular; it consists of comparison-exchange processing elements (PEs), routing paths, and short broadcast buses. Each bus contains a small number of simple switches that the authors call shift switches. They enhance and simplify the previously proposed shift switching mechanism to obtain an efficient O(1) VLSI-optimal sorting algorithm. From a theoretical perspective, the new approach reduces significantly both the number of PEs (from N/sup 2/ to N/sup 13/9/) and the number of broadcasts from more than 58 bus broadcasts, each over N switches, to at most 16 bus broadcasts, each over N/sup 4/9/ switches. From a practical standpoint, the network features a significant time-performance gain in comparison with the bitonic sorting circuit, especially when multiple smaller size arrays are sorted in parallel.<
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