High-speed circuit design with scaled-down MOSFETs and low supply voltage

The author investigates some of the points where circuit optimization with short-channel and low V/sub DD/ is different from the circuit optimization with long-channel and high V/sub DD/. Two effects are considered. The first effect is that in the short-channel MOSFET, the drain current dependent on gate voltage deviates from the Shockley's quadratic law and approaches linear law due to severe carrier velocity saturation. The other effect is that a threshold voltage of a MOSFET (V/sub TH/) cannot be scaled linearly with size reduction. The influences of the two effects are studied in a sense amplifier design and a SRAM cell design, respectively. A design strategy of a current-mirror sense amplifier (CMSA) for an embedded SRAM based on analytical formulas is given. It is shown that the voltage gain decreases due to the carrier velocity saturation. In the low V/sub DD/ regime, the CMSA suffers from a speed degradation and a current latch sense amplifier (CLSA) is shown to operate faster. For the SRAM cell design, an analytical expression is derived for a static noise margin (SNM) and it is shown that the SNM decreases by the velocity saturation.<
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