Synthesis of controllers from interval temporal logic specification

Presents a method which accepts interval temporal logic (ITL) formulas as a specification and automatically generates state machines. The specification in ITL can also be used as a constraint for a state machine that is an abstraction for an existing sequential circuit, which can be useful for redesign or engineering change. The generated state machines can be further processed by a logic synthesizer, such as SIS. We present experimental results and show the usefulness of our method.<
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