An efficient symbolic design verification system

Verifying the correctness of logic design has been an important problem for a long time. But there have been no efficient design verification tools for very large circuits. We present an efficient symbolic design verification method for very large circuits which exploits the properties of OPDDs (ordered partial decision diagrams). By symbolically extracting and simulating test patterns with OPDDs our design verification system provides time and space advantages over existing methods.<
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