Computer-aided redesign of VLSI circuits for hot-carrier reliability

In this paper a computer-aided design system for CMOS VLSI circuit hot-carrier reliability estimation and redesign is presented. The system first simulates circuits to determine the critical transistors that are most susceptible to hot-carrier effects (HCE); it then estimates the impact of HCE on circuit performance and employs a combination of design modification strategies to eliminate HCE degradation on the performance. The advantages and disadvantages of these alternative designs are also compared.<
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