A logic-level model for /spl alpha/-particle hits in CMOS circuits

Systems designed for reliability must be validated through simulations. However, traditional SPICE like simulators or even mixed-mode simulators are too slow for the task of simulating the effects of /spl alpha/-particle hits on relatively large circuits. Gate-level simulators offer tremendous speedup over these electrical level simulators, but they are only as good as the model which captures the /spl alpha/-particle effect at the logic level. The goal of this research is to develop a computationally efficient model which captures the behavior of the /spl alpha/-particle at the logic level. This model can then be used in a gate-level timing simulator to propagate the /spl alpha/-particle effects to the latches and the outputs of the circuit under simulation. We have developed a closed form solution to approximate the logic pulse waveform resulting from /spl alpha/-particle hits. As is presented in the paper, the model tracks the data from SPICE simulations remarkably well.<
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