Complex gate performance improvement by jog insertion into transistor gates

This paper describes how the insertion of 45 degree jogs into transistor gates leads to performance improvement of static CMOS complex gates. Therefore, CMOS complex gates were designed using a new layout style called Jogged Gate Matrix Layout (JOGM). SPICE3 simulation results exhibit an up to 44% speed improvement in comparison to traditional gate matrix layout style, due to reduced diffusion capacitances. JOGM also improves cell width by up to 31%.<
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