An overlay vernier and process bias monitor measured by voltage contrast SEM

A new type of vernier design which is digital in nature yet extremely dense is described. It does not require any functional circuitry to operate. Measurements can be made rapidly by simple inspection of the structure with scanning electron microscopy (SEM) operating in voltage contrast (VC) mode. This is achieved by designing a vernier where patterns either short or do not short to the wafer substrate, resulting in bright or dark regions (e.g. nonfloating or floating conductor regions) when viewed with a VC/SEM. Measurements of the location of the bright/dark interface region relate to the overlay and process bias of the monitor design levels on the wafer.<
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