An ECL to CMOS level converter with complementary bipolar output stage

A novel circuit scheme for the fast amplification of digital signals is presented. A fully complementary bipolar output stage realizes small delay and steep output signal slopes. The improved performance is achieved by intentionally saturating the bipolar output transistors, which allows one to supply the maximum current to the output. We evaluate the performance of saturated bipolar transistors fabricated on bulk silicon. Compared to known circuit schemes, the proposed circuit shows significantly reduced total delay and power dissipation. The driving capability for large capacitive loads is improved. Samples produced in a 2 /spl mu/m-BiCMOS technology verify the simulated performance.<
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