Spread and folded architectures for FFT

Computing a Fourier transform with a parallel architecture of serial operators needs a lot of implementation area to obtain the high performances promised with this method. Allocating processors to each step of the computation or computing only one step at the same time is one of the problems to solve. The degree of integration of up-to-date chips promises a realistic implementation of such solutions. Accuracy, area, computation time are the parameters to study before choosing a method in relation to the number of samples of the working space.<
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