Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications

A new active-pull-down nonthreshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an NMOS active-pull-down emitter-follower stage. A first-order analysis has been conducted to demonstrate the NMOS-APD concept. Simulation results based on 0.6 /spl mu/m BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4/spl times/ improvement in the load driving capability and 3.4/spl times/ improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV.<
>