On self-checking design of CMOS circuits

A technique that enables the design of total self checking (TSC) FCMOS circuits for all realistic defects that may occur in VLSI circuits is discussed. The resulting area overhead is very low. The technique is unable to detect multiple defects which include the weak transistors. This condition can be alleviated by adding more weak transistors in parallel to the existing ones. This redundancy does increase the overhead, but may be justifiable in certain cases. Simulation results show the introduction of a small delay in the circuit due to the two weak transistors. This delay can be further minimized by proper choice of the transistor sizes. The defects covered by this technique and the low overhead makes it practical for self checking VLSI circuit design.<
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