High level testability analysis using VHDL descriptions

Tests generated for modules in a design may not be applicable from the design boundaries due to global constraints. The authors discuss high level techniques that can be used to analyze a sequential circuit and precompute useful information that reflects the controllability of inputs and observability of outputs of modules in the design. The information can then be used in conjunction with the tests generated for modules to obtain high quality tests for the design quickly. Results obtained for example circuits are presented to demonstrate the techniques.<
>