Technology mapping of mixed polarity Reed-Muller representations

There is interest in using Reed-Muller forms (exclusive-OR sums of products) as a representation in logic synthesis. There are algorithms available for two-level and multilevel minimization, but there is a lack of techniques for sum of products technology mapping. Two methods are presented: a simple rule-based method which decomposes the representations until they match a gate in the library; and a more sophisticated directed acyclic graph (DAG) mapping method which covers a directed acyclic graph representation of the network with DAG representations of gates from the gate library. Both methods have been implemented, and full sets of results are given. A number of suggestions are made for improving both methods.<>