Functional timing analysis using ATPG

The authors show how unmodified conventional Automatic Test Pattern Generators (ATPG) for such faults can be used for functional timing analysis without sacrificing computational efficiency in comparison with existing approaches to the same problem. This is a significant result since it permits use of the entire body of work in ATPG for this problem. The procedure can handle any delay model used in logic synthesis and simulation, making it applicable at any level of circuit abstraction during logic synthesis. Preliminary experimental results are presented to show that not only is the proposed procedure practical but in fact is significantly better than competing approaches on troublesome circuits.<>