Design of a discrete cosine transform circuit using the residue number system

The design of an integrated circuit aimed at efficient discrete cosine transform computation is presented. High performance is obtained through the use of pipelining and residue arithmetic. An approach to high-speed modular multiplication employing the periodic properties of powers of two taken modulo A is reported. The test chip is implemented using the ES2 1.5-/spl mu/m CMOS process, has a die size of 29.55 mm/sup 2/ and dissipates 140 mW of power. The maximum throughput is in excess of 30 MHz.<
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