Performance-oriented technology mapping for LUT-based FPGA's

An efficient and effective optimization technique is developed for technology mapping of lookup table (LUT) based field programmable gate arrays. In our algorithm, minimal depth of a Boolean network is found and then the given cost function is minimized by "sweeping" nodes of the given Boolean network without increasing the depth. The sweeping allows an efficient search over a huge solution space since it utilizes the topological structure of the network. Optimization for reconvergent paths and duplication of logic can be automatically considered during the sweeping procedure. Experimental results show that our approach is very promising. Typically our method, called SWEEP, produced the same depth for the 17 benchmark circuits tried as those of FlowMap which guarantees the optimum depth. Furthermore, SWEEP outperforms FlowMap by 17% in the total number of LUT's required to implement the benchmark circuits.<
>