Testability implications of performance driven logic synthesis

Retiming improves performance but also increases test generation time and decreases fault coverage. Research conducted at Carnegie Mellon and McGill Universities attempts to explain the impact of retiming on the testability of sequential logic circuits. A novel test preservation theorem suggests a powerful way to decrease the test generation cost of retimed circuits. The authors also discuss a recently recognized circuit attribute that better explains the complexity of structural, sequential automatic test pattern generation.<
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