Modeling the polysilicon depletion effect and its impact on submicrometer CMOS circuit performance

We present a physically based continuous analytical MOSFET model for submicrometer devices that includes polysilicon depletion effect. It is shown that simple modification to standard MOSFET circuit models is all that is needed to account for the polydepletion effect. The new model accurately predicts, both measured and 2-D simulated, I-V, and C-V characteristics of submicrometer MOSFET's with polydepletion effect over a range of polysilicon gate concentration, N/sub p/, down to 5/spl times/10/sup 18/ cm/sup 3/. It is found that neglecting the polydepletion effect for devices with nondegenerate gate doping leads to nonphysical model parameters and causes large errors in the capacitance modeled results. The new model has been implemented in the circuit simulator SPICE. Since both device current and capacitance degrade due to polydepletion effect, its impact on circuit performance is studied using inverter type circuits with different loading conditions. SPICE simulations show that for 0.35 /spl mu/m CMOS technology (gate oxide thickness, t/sub ox/=70 /spl Aring/) the increase in the delay time for chain of inverters is 3.5% for N/sub p/=2/spl times/10/sup 19/ cm/sup -3/ (for both nand p-channel devices) compared to N/sub p/=5/spl times/10/sup 19/, cm/sup -3/. For a given t/sub ox/ and nondegenerate value of N/sub p/, lowering the channel length helps to reduce the polydepletion effect and hence circuit performance degradation. However, reducing the power supply, for low power operation, enhances the polydepletion effect.<
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