A 50 MHz 70 mW 8-tap adaptive equalizer/Viterbi sequence detector in 1.2 /spl mu/m CMOS

A new architecture for digital implementation of the adaptive equalizer in Class IV Partial Response Maximum Likelihood (PRML) channels employing parallelism and pipelining is described. The architecture was used in a prototype integrated circuit in a 1.2 /spl mu/m CMOS technology to implement a 50 MHz adaptive equalizer and Viterbi sequence detector dissipating 70 mW from a 3.3 V supply.<
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